The computational demands of artificial intelligence have reached a scale that semiconductor arithmetic capacity alone can no longer support. In modern large-scale clusters, an amount of engineering attention equal to or greater than the time GPUs spend on computation is devoted to data movement.
When integrating tens of thousands to hundreds of thousands of accelerators, system performance is not determined by the FLOPS of individual chips. The effective performance is dictated by the bandwidth, latency, power consumption, and signal integrity of the information flowing between GPUs, HBM, switches, racks, and data centers.
This constraint is the “wire problem.”
The copper tax
Copper wiring possesses resistance, parasitic capacitance, and parasitic inductance. As transmission frequencies rise, conductor losses and dielectric losses increase, shrinking signal amplitude, eye openings, and timing margins. Extending the distance only worsens the situation.
High-speed electrical links reconstruct signals using SerDes, equalizers, retimers, clock recovery circuits, and DSPs. This circuitry does not compute data; it consumes power merely to deliver data to the next processing element.
As AI clusters grow, this transport tax compounds iteratively. Power is converted into heat through wiring losses, burdening cooling infrastructure and driving up the power density of the entire facility. Even if adding GPUs increases theoretical performance, utilization will not rise unless the communication fabric can keep pace.
This problem cannot be solved by miniaturization alone. Transistor improvements and the physics of interconnects advance at different speeds.
Light rewrites distance
Silicon photonics encodes information into the intensity, phase, polarization, and wavelength of light. Light propagates through on-chip waveguides and passes through modulators, resonators, interferometers, and photodetectors.
Optical waveguides do not suffer from the same resistive loss mechanisms as electrical wiring. Transmission loss still exists. Laser power is required. Coupling losses, scattering, thermal drift, and detection noise cannot be ignored. Nevertheless, the energy scaling for transporting high-bandwidth signals over long distances can become favorable compared to copper.
With wavelength-division multiplexing, a single waveguide can accommodate multiple optical carriers. Each wavelength acts as an independent data channel, enabling total bandwidth expansion without a dramatic increase in wiring footprint. In photonic matrix operations, designs that leverage wavelength, space, time, and mode as parallel degrees of freedom are also under investigation. (Nature)
Light does not eliminate electronic circuits. Electronics will remain for control, memory, nonlinear operations, error correction, and data conversion. What changes is the boundary of the electrical domain. By shortening long electrical links and shifting the high-bandwidth segments to light, the overall thermodynamics of the system can be improved.
I/O changes first
The clearest near-term progress in the commercialization of photonics is in GPU-to-GPU communication, switch-to-switch communication, and off-package I/O.
Co-packaged optics place optical engines in close proximity to switch ASICs or compute packages. This reduces the distance electrical signals must traverse across long board traces, converting to light near the package. NVIDIA has announced silicon photonics switches in the Spectrum-X and Quantum-X lines, emphasizing lower power consumption, higher density, and lower latency compared to traditional pluggable optical transceivers. Their technical materials show a 3.5× improvement in power efficiency for certain switch configurations. (NVIDIA)
Lightmatter’s Passage should not be categorized as an optical compute accelerator. Its current primary focus is a 3D photonic interconnect. It is designed as a platform to connect chiplets, multi-die, and wafer-scale configurations with high-bandwidth optical links. (Lightmatter®)
Ayar Labs integrates optical interfaces into compute packages using TeraPHY optical I/O chiplets and external light sources. The goal is to connect multiple GPUs or XPUs into a high-bandwidth, low-latency fabric, operating them as a single giant logical accelerator. (Ayar Labs)
The important point is not the product names. Optical connectivity is moving from an external network technology outside the rack to an architectural element inside the package.
Matrix math as light
The principal computational load of machine learning is concentrated in matrix multiplications, convolutions, and the linear transformations inside attention mechanisms. These operations are executed as a massive number of multiply-accumulate operations on electronic circuits.
Photonic processors exploit the linear transformation of electromagnetic fields as matrix operations. In a mesh of Mach–Zehnder interferometers, combinations of phase shifters and beam splitters implement unitary transformations. In a weight bank of microring resonators, the per-wavelength transmittance acts as a matrix element. In diffractive systems, free-space propagation and phase masks form linear operators.
The very passage of light through a circuit becomes the computation. There is no need to charge and discharge every multiplier on every clock cycle; wavelength multiplexing and spatial parallelism can be utilized simultaneously.
Experimental studies have demonstrated optical vector inner products operating in a regime where the detection energy averages less than one photon. This indicates the physical efficiency limits of optical matrix operations, not a figure that represents the total power consumption of a complete AI system. (Nature)
A single number like “optical computing can cut power consumption by 90%” cannot be used as a general design rule. A real energy budget includes lasers, modulators, photodetectors, DACs, ADCs, memory access, calibration, and thermal control. Even if the optical core is extraordinarily efficient, repeating electrical-to-optical conversion at every layer erases the advantage.
The metric that determines practicality is not the TOPS/W of the optical core alone. It is tokens per joule when executing an entire model, end-to-end latency, accuracy preservation, recalibration frequency, and manufacturing yield.
Manufacturing is the hard part
The research principles of photonics are well established. Volume production technology remains difficult.
Coupling lasers to silicon waveguides, aligning fiber arrays, bonding dissimilar materials, thermal expansion mismatches, wavelength drift of resonators, in-package power delivery, testing processes, and reparability all determine product cost. Nanometer-scale structural errors shift phase responses and resonant wavelengths, meaning that design values are not always maintained after manufacturing.
Calibration software is not an auxiliary function. It is an effective part of a photonic device.
In 2026, NVIDIA announced multi-year agreements with Lumentum and Coherent. The centerpiece of these contracts is R&D, laser supply, and the expansion of U.S.-based manufacturing capacity. Lumentum has indicated plans to invest hundreds of millions of dollars in U.S. manufacturing sites for AI data center lasers, while Coherent is expanding wafer fabrication capacity for InP photonic devices. (NVIDIA Newsroom)
This goes beyond component procurement. It is the buildup of an industrial base that makes gigawatt-scale AI facilities viable.
Unbundling the server
When the distance constraints of copper links are relaxed, the need to confine GPUs, memory, storage, and networking equipment within fixed server units decreases.
Compute resources can shift into rack-scale shared pools. Configurations that dynamically allocate accelerators, HBM capacity, and network bandwidth according to workload become practical. Designs that logically isolate faulty components and continue jobs with remaining resources also become easier.
This resource disaggregation is not a technique for increasing the amount of computation. It is a technique for connecting existing compute resources at higher utilization. We are entering a phase where large-model training speed, inference cost, and cluster availability depend more strongly on fabric design than on the performance of individual chips.
Nanarch’s perspective
The next advance in machine learning infrastructure will not arise from model architectures alone. It will require designing materials, waveguides, modulators, packages, compilers, calibration systems, and network topologies as a single computer.
Nanarch does not view photonics as a high-speed wiring component. We treat the propagation, interference, dispersion, resonance, and nonlinear response of light as computational resources. Traditional abstractions that hide hardware physics from software are insufficient in this domain.
The wire problem began as a question of wiring materials. It is now a question of system architecture.
If photonics succeeds, the fundamental unit of AI infrastructure will shift from the individual GPU server to a distributed computational medium coupled by an optical fabric. What will determine the next generation of performance competition is not merely transistor count.
In which physical medium, over what distance, and at how low an energy cost can we carry information?
That question defines the next era of machine learning infrastructure.